The present invention relates to a semiconductor device in which a plurality of semiconductor chips differing in withstand voltage or a plurality of semiconductor differing in chip noise immunity are stacked one over another, such as a multi-chip module (MCM). More particularly, it relates to a technique which can be effectively applied to system-in-package (SIP) semiconductor devices which perform, for instance, analog front end processing for the outputs of charge-coupled devices (CCDs) and pulse driving for CCDs.
Known multi-chip modules in which a plurality of semiconductor chips differing in noise immunity are stacked one over another include one in which individually formed analog chips and digital chips are integrated into a single package is described in Patent Document 1. By separating analog chips and digital chips from each other, the analog circuits are protected from being affected via a common silicon substrate by noise occurring in the digital circuits. The arrangement of the analog chips smaller in chip size over the digital chips contributes to reducing the module size.
Patent Document 2 describes a multi-chip module in which a plurality of semiconductor chips are stacked one over another, over a package substrate. The semiconductor chips are electrically connected to the package substrate via bonding wires. The semiconductor chips arranged in lower layers are wire-bonded to positions away from the edges of the package substrate while those arranged in upper layers are wire-bonded to positions closer to the edges of the package substrate.
Patent Document 1: Japanese Translation of Unexamined PCT application No. 2004-523912
Patent Document 2: Japanese Unexamined Patent Application Laid-Open No. 2004-111656